1. Field
Exemplary embodiments of the present invention relate to a semiconductor device capable of controlling impedance.
2. Description of the Related Art
Semiconductor devices may include systems and features to accurately control the duty cycle of a clock in a clock-based system. The duty cycle of a clock is the ratio of high-pulse duration or low-pulse duration to the period of the clock. Recent memory devices, particularly, a Double Data Rate (DDR) synchronous memory device, use clocks, for example, for data strobe. Two-bit data is inputted and outputted consecutively in synchronization with a rising edge and a falling edge of a clock. If the duty cycle of a clock does not maintain approximately 50%, inputted and outputted data may be distorted. Therefore, it is important to accurately control the duty cycle of a clock in a memory device.
A clock inputted into a memory device is generated in an external clock generator and transferred to the memory device through a transfer line. In this configuration, the duty cycle of a clock is may be distorted because the high-pulse duration and the low-pulse duration of a clock become different due to mismatch of a clock generator, external noise during the transferring, and attenuation of the amplitude of an electrical signal on the transfer line. To control the duty cycle of the clock, a duty cycle corrector for correcting the duty cycle may be used in a memory device. However, even if the duty cycle corrector is used, it is difficult to maintain the duty cycle at 50% due to on-chip power noise.